1. Field of the Invention
The present invention relates to a semiconductor integrated circuit pattern verification method capable of efficiently performing pattern verification, a photomask manufacturing method, a semiconductor integrated circuit device manufacturing method, and a program for implementing a semiconductor integrated circuit pattern verification method.
2. Description of the Related Art
Recent progress of the semiconductor manufacturing technique is very remarkable, and semiconductor elements micropatterned to a minimum feature size of 70 nm are mass-produced. Micropatterning is realized by rapid improvement of the pattern formation technique including mask process, photolithography, and etching.
When the pattern size of a semiconductor integrated circuit is large enough, the planar shape of a desired circuit pattern to be formed on a wafer is drawn as a design pattern as it is, and a mask pattern faithful to the design pattern is formed. The mask pattern is transferred onto a wafer through a projection optical system, and the substrate is etched to form almost the same pattern as the design pattern on the wafer.
However, as the patterns of semiconductor integrated circuits shrink in feature size, it becomes difficult to faithfully form a pattern by each process. The final dimension on a resultant wafer undesirably becomes different from the design pattern.
Especially in lithography and etching processes which are the most important in achieving micropatterning, the layout of patterns near a pattern to be formed greatly influences the dimensional accuracy of the pattern to be formed.
To cancel the influence of these processes, so-called OPC (Optical Proximity Correction) and PPC (Process Proximity Correction) have been developed. These techniques perform pattern correction in advance by adding a supplement pattern or increasing/decreasing the pattern width so as to adjust the dimension after processing to a desired design pattern. These techniques are reported in Jpn. Pat. Appln. KOKAI Publication Nos. 9-319067 and 2003-107664, and SPIE Vol. 2322 (1994) 374 (D. M. Newmark et al., Large Area Optical Proximity Correction using Pattern Based Correction).
These techniques can form on a wafer a semiconductor integrated circuit pattern drawn by the designer, but require verification of whether pattern correction by OPC and PPC has been performed correctly. In order to verify the accuracy of correction, verification may be done on the basis of the mask value. However, verification using a (lithography) simulator is indispensable for accurately executing verification.
For example, U.S. Pat. No. 6,470,489 discloses a verification tool which compares the edge of a desired pattern on a wafer with that of a pattern transferred using a layout after OPC, and checks whether the difference between these edges falls within a predetermined allowance.
Jpn. Pat. Appln. KOKAI Publication No. 9-319067 proposes a method of predicting at high precision a positional deviation between the edge of a desired pattern and that of a transferred pattern by using the same physical model for proximity correction and verification.
According to the prior arts, when patterns of the same type exist in one verification area, they are all detected. Thus, the number of detection portions is large, and it is very difficult to execute review (confirm portions at which patterns are detected).